Intel Many Integrated Core (MIC) architecture and the UnTRIM code

Intel Many Integrated Core (MIC) architecture and the UnTRIM code, 11th UnTRIM Workshop, Trento, 19-21 May 2014.

The presentation describes the results of an investigation concerning the potential of porting the UnTRIM2 code (with subgrids, see Casulli and Stelling 2010) to the Intel MIC processors, the trade mark name Xeon Phi. Comparisons between runs without changing the present UnTRIM2 code applying the existing MPI-, OpenMP- and hybrid parallelisations are provided. Specific aspects concerning the vectorisation and thread placement are discussed. An outlook concerning the possible adaptations to the future processors is given.

Transparencies are available.

There exists an internal technical report concerning this investigation.