Developments concerning the parallel input and output (IO) in the parallel version of UnTRIM with a special attention for its efficiency are presented. The usage of MPI IO (developed ca. 2010) and of the highly specialised libraries like HDF5 or NetCDF (developments in 2018 and 2019) is discussed and assessed from the point of view of engineering practice and the efficiency of parallel IO systems ubiquitous in the present-day high performance computers.
Transparencies for a talk presented on 16th UnTRIM Workshop held in Trento, 13-15th May 2019 are available.
E. Rustico, J. Jankowski, A. Hérault, G. Bilotta and C. Del Negro
Abstract: We present a restructured version of GPUSPH, a CUDA-based implementation of SPH. The new version is extended to allow execution on multiple GPUs on one or more host nodes, making it possible to concurrently exploit hundreds of devices across a network, allowing the simulation on larger domains and at higher resolutions. Partitioning of the computational domain is not limited anymore to parallel planes and can follow arbitrary, user-defined shapes at the resolution of individual cells, where the cell is defined by the auxiliary grid used for fast neighbor search. Continue reading
Intel Many Integrated Core (MIC) architecture and the UnTRIM code, 11th UnTRIM Workshop, Trento, 19-21 May 2014.
The presentation describes the results of an investigation concerning the potential of porting the UnTRIM2 code (with subgrids, see Casulli and Stelling 2010) to the Intel MIC processors, the trade mark name Xeon Phi. Continue reading
Jacek A. Jankowski
This technical report (in German) concerns the assessment of porting feasibility of codes UnTRIM2 and Telemac to the Intel Xeon Phi, i.e. MIC (Many Integrated Cores) architecture. German abstract follows. Continue reading