Tag Archives: UnTRIM

Parallel IO for parallel UnTRIM

Developments concerning the parallel input and output (IO) in the parallel version of UnTRIM with a special attention for its efficiency are presented. The usage of MPI IO (developed ca. 2010) and of the highly specialised libraries like HDF5 or NetCDF (developments in 2018 and 2019) is discussed and assessed from the point of view of engineering practice and the efficiency of parallel IO systems ubiquitous in the present-day high performance computers.

Transparencies for a talk presented on 16th UnTRIM Workshop held in Trento, 13-15th May 2019 are available.

Ten Years After: MPI-UnTRIM’s past and future

The presentation summarizes in a rather informal and philosophical, but thoroughly informative way the development history of the MPI version of UnTRIM ten years after finalizing the parallel code applied subsequently for practical projects at BAW.

Transparencies from the talk delivered on 15th UnTRIM Workshop in Trento (28-30th May 2018) are available.

Efficient river modelling applying subgrid technology (UnTRIM2)

Two subsequent presentations on the 13th UnTRIM Workshop 2016 with the same title Efficient river modelling applying subgrid technology (UnTRIM2), the first part concerning concept and grids, presented by Regina Patzwahl, and the second part concerning results, presented by Jacek A. Jankowski. Continue reading

Intel Many Integrated Core (MIC) architecture and the UnTRIM code

Intel Many Integrated Core (MIC) architecture and the UnTRIM code, 11th UnTRIM Workshop, Trento, 19-21 May 2014.

The presentation describes the results of an investigation concerning the potential of porting the UnTRIM2 code (with subgrids, see Casulli and Stelling 2010) to the Intel MIC processors, the trade mark name Xeon Phi. Continue reading

Potential der Intel Many Integrated Core Architektur für die Flussmodellierung — Codes UnTRIM und Telemac

Jacek A. Jankowski

This technical report (in German) concerns the assessment of porting feasibility of codes UnTRIM2 and Telemac to the Intel Xeon Phi, i.e. MIC (Many Integrated Cores) architecture. German abstract follows. Continue reading